Job Detail

Principal Design Engineer - Microsoft Corporation
Austin, TX
Posted: Nov 16, 2022 05:03

Job Description

Principal Design Engineer , Physical Design

Microsoft's hardware teams incubate advanced technologies and build deep partnerships with internal research, product planning, business and marketing teams. Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Our opportunities represent a variety of disciplines including, but not limited to, design, verification, performance modeling, and DevOps supporting the development of custom silicon. Microsoft's hardware teams are also expanding into new technologies such as quantum computing!

Responsibilities

The SILICON COMPUTING DEVELOPMENT TEAM is seeking passionate, driven and intellectually curious engineers to join our physical-design SoC design team covering RTL to GDS methodology, design convergence, and design quality for our projects. This new team will be involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner. In this high impact role on the team, you will be responsible to:

  • Complete netlist to GDS2 implementation for PPA focused & challenging very highfrequency partitions/blocks meeting schedule with design goals.

  • Own and drive floor-planning and design planning with execution for optimizinglarge sub-chips and full chip for Area, Power and Performance.

  • Experience with Leading Edge SOC Architecture and Landing Zone requirements particularly with high-speedfabric and overall protocol and connectivity models.

  • Have close collaboration with RTL, Arch, and Performance model teams to help drive, plan and resolve design issues.

  • Own and drive execution from synthesis to tapeout signoff of large sub-chips and/or full chip.

  • Influence tools, flows, and overall design methodologyin design construction, signoff, and optimization with a data driven approach.

  • Lead and engage inrequired synthesis to gds2 tool, flows & methodology working with cad team.

  • Clear communications with presentations on project status & planning.

  • Make good independent technical trade-offs between power, area, and timing.

  • Provide technical leadership and collaborate across teams (cross sites) to come up with the best solution possible with a One Microsoft mindset.

Qualifications

Requiremen ts :

  • BS/MS in Electrical or Computer Engineering with 8+ years of experience.

  • You should have demonstrated physical design (synthesis, pnr & timing closure) experience, with recent successful tapeouts in deep submicron technology & in high-frequency designs.

  • Proven understanding of PD construction & analysis flows and methodology.

  • Shown ability to execute stringent schedule & die size requirements.

  • Deep understanding and experience with scripting language such as python/perl/tcl.

  • Great communication, collaboration, teamwork skills and ability to contribute to diverse and inclusive teams.

  • Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.

  • Strong understanding of constraints generation, STA, timing optimization, and timing closure.

  • In-depth understanding of design tradeoffs for power, performance, and area.

  • Solid hands-on experience with CTS and global clock distribution methods in multi-voltage, multi-clock, multi-domain, and low power designs.

  • Experience in EDA tools such as Primetime, StarRC, Design Compiler, FC, Innovus, Cadence & Synopsys PnR tools etc.

  • Experience and knowledge of formal equivalency checks, LP, UPF, reliability, SI, and noise.

  • Strong problem-solving and data analysis skills.

Additional Preferred one or more of these Requirements :

  • Full Chip/Sub Chip design planning experience using industry standard EDA tools.

  • Large SoC design tape-out experience in the latest foundry process nodes.

  • Excellent project management skills and ability to juggle multiple projects at once.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form (https://careers.microsoft.com/us/en/accommodationrequest) .

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.



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