SoC Physical Design Engineer (Starlink) at SpaceX
Mountain View, CA, United States
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SOC PHYSICAL DESIGN ENGINEER (STARLINK)
As a member of our multifaceted ASIC team, you will have the rare and phenomenal opportunity to craft upcoming SOCs that will enable our Starlink chips. These chips help connect, enable, and empower humanity every single day with performance that far surpasses that of traditional satellite internet and ground infrastructure limitations. Starlink delivers high-speed, low latency broadband internet to locations where access has been unreliable, expensive, or completely unavailable.
In this critical role, as a SOC/ASIC physical design engineer, you will be collaborating with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge SoCs for customers on Earth and beyond. We are looking for people who want to dive in and get their hands dirty and push the limits of what is possible through innovation, determination, and teamwork.
RESPONSIBILITIES:
Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
Develop/improve physical design methodologies and automation scripts for various implementation steps
Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
BASIC QUALIFICATIONS:
Bachelor's degree in electrical engineering, computer engineering or computer science
2+ years of ASIC and/or physical design flow development experience (internship and collegiate extracurricular engineering project experience qualifies)
PREFERRED SKILLS AND EXPERIENCE:
Basic experience of ASIC/SOCs RTL2GDSII physical design and signoff flows
Basic experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
Knowledge of deep sub-micron FinFET and CMOS solid state physics
Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
Familiar with CMOS analog circuit and physical design
Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
Must be willing to travel when needed (typically <10%)
Willing to work extended hours and weekends to meet critical deadlines, as needed
This position can be based in either Redmond, WA, Irvine, CA, or Mountain View, CA
ITAR REQUIREMENTS:
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.
