Principal SOC EMIR & Power Integrity Engineer (Silicon Engineering) at SpaceX
Mountain View, CA, United States
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
PRINCIPAL SOC EMIR & POWER INTEGRITY ENGINEER (SILICON ENGINEERING)
As a member of our multifaceted ASIC team, you will have the rare and phenomenal opportunity to craft upcoming SOCs that will enable our Starlink chips. These chips help connect, enable, and empower humanity every single day with performance that far surpasses that of traditional satellite internet and ground infrastructure limitations. Starlink delivers high-speed, low latency broadband internet to locations where access has been unreliable, expensive, or completely unavailable.
In this critical role, as an SOC EMIR and Power Integrity engineer, you will be collaborating with physical design, timing, and logic design teams making a crucial impact on delivering cutting edge SOCs for customers on Earth and beyond. We are looking for people who want to dive in and get their hands dirty and push the limits of what is possible through innovation, determination and teamwork.
RESPONSIBILITIES:
Develop and support block and full chip automated static and instantaneous voltage (IR) drop, signal electromigration (EM) flows
Responsible for block and full chip static/dynamic EMIR, rush current, DFT (Design For Test) IR, analysis and chip power model
Collaborate with package, architecture and physical design teams to create power distribution network (PDN), improve padring, bump and redistribution layer (RDL) design
Define modes and corners for functional/scan shift static voltage, instantaneous voltage and EM analysis
Package modeling and analysis, chip package co-design for high performance processing
Closely collaborate with physical design and timing signoff team members to enable IR drop aware timing flows
BASIC QUALIFICATIONS:
Bachelor's degree in electrical engineering, computer engineering or computer science
10+ years of experience working with block or full chip voltage drop and/or power/signal electro-migration analysis
PREFERRED SKILLS AND EXPERIENCE:
Experienced in industry standard tools used for EM/IR Drop such as RedHawk, Voltus, etc.
Experience in developing for block and full chip level IR Drop and EM analysis flows
Knowledge in high frequency power integrity simulation and analysis
Experience in IP integration (e.g. memories, I/O's, Analog IPs, SerDes, DDR etc.)
Proven experience in silicon (on-chip) and package power delivery network principles
Strong knowledge of deep sub-micron FinFET technology nodes (7nm and below) and design challenges
Experience with high reliability design and implementations
Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
Must be willing to travel when needed (typically <10%)
Willing to work extended hours and weekends as needed, to meet critical deadlines
This position can be based in either Redmond, WA, Irvine, CA, or Mountain View, CA
ITAR REQUIREMENTS:
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.
