Principal SOC Physical Design Engineer at SpaceX
Irvine, CA, United States
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
PRINCIPAL SOC PHYSICAL DESIGN ENGINEER (STARLINK)
As a member of our multifaceted ASIC team, you will have the rare and phenomenal opportunity to craft upcoming SOCs that will enable our Starlink chips. These chips help connect, enable, and empower humanity every single day with performance that far surpasses that of traditional satellite internet and ground infrastructure limitations. Starlink delivers high-speed, low latency broadband internet to locations where access has been unreliable, expensive, or completely unavailable.
In this critical role, as a full chip SOC/ASIC physical design engineer, you will be collaborating with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge SOCs for customers on Earth and beyond. We are looking for people who want to dive in and get their hands dirty and push the limits of what is possible through innovation, determination, and teamwork.
RESPONSIBILITIES:
Perform SOC full chip physical design; floor-planning, I/O, bump & RDL (Redistribution layer) planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, partition hardening, chip level clock, feedthrough, special interface, and interconnect planning, bus routing, sequential pipeline planning and full chip design for testability (DFT) planning
Collaborate with chip architects, ASIC engineers, package engineers and block level physical design engineers to drive, chip floorplan reviews and identify area, interconnect, IP integration, and floorplan improvement opportunities
Perform full chip timing budgeting and constraint pushdown to partition owners
Work with static timing analysis, physical verification, electromigration/voltage drop, noise and other signoff teams to achieve closure and tapeout on time
Run physical verification at chip level and provide feedback and guidance to block level physical design engineers to fix design rule check/layout versus schematic/antenna/electrical rule check/design for manufacturing violations
Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements
BASIC QUALIFICATIONS:
Bachelor's degree in electrical engineering, computer engineering or computer science
10+ years of ASIC full chip tapeout and/or physical design flow development experience
PREFERRED SKILLS AND EXPERIENCE:
Experience and deep understanding of SOC full chip physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
Experience in IP integration (e.g. memories, I/O's, analog IPs, SerDes, DDR etc.)
In-depth knowledge of industry standard EDA tools, understand their capabilities and underlying algorithms
Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHZ
Strong knowledge of deep sub-micron FinFET technology nodes (7nm and below) design problems and solutions (leakage power, signal integrity, etc.) multi-corner and multimode timing closure, process variations, physical verification methodology and tapeout
Familiar with implementation or integration of design blocks using Verilog/System Verilog
Experience with clock domain crossings, DFT/Scan/MBIST/LBIST/JTAG/Boundary-scan testing and understanding impacts on physical design flow
Experience with high reliability design and implementations
Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
Must be willing to travel when needed (typically <10%)
Willing to work extended hours and weekends to meet critical deadlines, as needed
This position can be based in either Redmond, WA or Irvine, CA
ITAR REQUIREMENTS:
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.
