Sr. SOC DFT Design Engineer (Starlink) at SpaceX
Mountain View, CA, United States
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. SOC DFT DESIGN ENGINEER (STARLINK)
As a member of our multifaceted ASIC team, you will have the rare and phenomenal opportunity to craft upcoming SOCs that will enable our Starlink chips. These chips help connect, enable, and empower humanity every single day with performance that far surpasses that of traditional satellite internet and ground infrastructure limitations. Starlink delivers high-speed, low latency broadband internet to locations where access has been unreliable, expensive, or completely unavailable.
In this critical role, as an SOC/ASIC DFT (Design for Testability) Design engineer, you will be collaborating with architecture, timing, and logic design teams making a crucial impact on delivering cutting edge SOCs for customers on Earth and beyond. We are looking for people who want to dive in and get their hands dirty and push the limits of what is possible through innovation, determination, and teamwork.
RESPONSIBILITIES:
Develop/support automated block and full chip level DFT insertion flows and incorporate those flows into Physical design infrastructure
Evaluate design readiness for scan insertion through RTL and physical design
Run and evaluate scan insertion through synthesis tools and refine scan insertion recipes for maximum coverage
Responsible for full chip test insertion, IEEE 1500, JTAG, boundary scan, block level MBIST/on chip clock controller insertion
Run ATPG (Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals
Drive Scan/ATPG low coverage debug
Integrate and verifiy DFT fabrics and IP within subsystems
Scan timing closure, scan shift/scan capture mode timing constraint development
Create ATPG vectors for use in post-silicon testing and validation of that content through gate level simulations
Collaborate with circuit physical design team, ATPG team, and manufacturing team to facilitate high quality scan and memory BIST coverage in silicon
BASIC QUALIFICATIONS:
Bachelor's degree in electrical engineering, computer engineering or computer science
5+ years of experience working as block and full chip design for test (DFT) engineer
PREFERRED SKILLS AND EXPERIENCE:
Experience in DFT specifications, architecture, integration, methods and validation
Knowledge about industrial standards, tools, and practices in DFT; including ATPG, JTAG, MBIST, LBIST and trade-offs between test quality and test time
Verilog/SystemVerilog and DFT design verification methods, simulators and waveform debugging tools
Experience in debugging compressed ATPG, MBIST and JTAG related issues
Experience in STA constraints development and analysis for DFT modes and SDF simulations
Ability to conduct experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data
Knowledge of ASIC synthesis, physical design flows, methodologies, clock domain crossing challenges and understanding DFT impact on those flows and tapeout signoff
Experience to understand, trace, and debug RTL connectivity issues as they pertain to DFT
Experience with unified power format, formal verification and DRC rule checking experience
Knowledge of deep sub-micron FinFET technology nodes (7nm and below) and DFT challenges associated with them
Experience with high reliability design and implementations
Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
Must be willing to travel when needed (typically <10%)
Willing to work extended hours and weekends to meet critical deadlines, as needed
This position can be based in either Redmond, WA, Irvine, CA, or Mountain View, CA
ITAR REQUIREMENTS:
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.
