Sr. SoC Physical Verification and Physical Integration Engineer (Starlink) at SpaceX
Irvine, CA, United States
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. SOC PHYSICAL VERIFICATION AND PHYSICAL INTEGRATION ENGINEER (STARLINK)
As a member of our multifaceted ASIC design team, you will have the rare opportunity to craft upcoming SOCs that will enable our Starlink chips. These chips help connect, enable, and empower humanity every single day with performance that far surpasses that of traditional satellite internet and ground infrastructure limitations. Starlink delivers high-speed, low latency broadband internet to locations where access has been unreliable, expensive, or completely unavailable.
In this critical role, as an SOC physical verification and integration engineer, you will be collaborating with physical and package design teams making a crucial impact on delivering cutting edge SOCs for customers on Earth and beyond. We are looking for people who want to dive in and get their hands dirty and push the limits of what is possible through innovation, determination, and teamwork.
RESPONSIBILITIES:
Develop and support block and full chip automated physical verification (PV) flows and scripts
Perform block and full chip physical verification and work with physical design (PD) team to close design issues
Execute SOC GDSII integration, seal ring addition and tapeout collateral generation to send to the foundry
Work closely with semiconductor foundries on installation, maintenance of process design kits (PDKs) for SOC physical design teams
Be the bridge between physical design team and the foundry, doing PV electronic design automation (EDA) tool support across all silicon projects
BASIC QUALIFICATIONS:
Bachelor's degree in electrical engineering, computer engineering or computer science
5+ years of experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support
PREFERRED SKILLS AND EXPERIENCE:
Experience in industry standard physical verification EDA tools
Experience in developing block and full chip physical verification flows for Design Rule Check (DRC)/Layout Versus Schematic (LVS)/Antenna (ANT)/Electrical Rule Check (ERC)/Design for Manufacturing (DFM)/Electrostatic Discharge (ESD) etc.
Experience in top-level integration of connectivity, system bus, peripherals and CPU IP
Experience in ASIC physical design and strong experience in mixed-signal IP integration
Proficiency in writing Linux shell scripts and general programming (e.g., Perl, shell, TCL and/or Python)
Experience working with foundry, installing PDKs, libraries, IPs and setting up design environments for PD teams
Strong knowledge of deep sub-micron FinFET technology nodes (7nm and below)
Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
Must be willing to travel when needed (typically <10%)
Willing to work extended hours and weekends as needed, to meet critical deadlines
This position can be based in either Redmond, WA or Irvine, CA
ITAR REQUIREMENTS:
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.
