Sr. SOC Synthesis & Front-End STA Engineer at SpaceX
Irvine, CA, United States
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. SOC SYNTHESIS & FRONT-END STA ENGINEER (STARLINK)
As a member of our multifaceted ASIC team, you will have the rare and phenomenal opportunity to craft upcoming SOCs that will enable our Starlink chips. These chips help connect, enable, and empower humanity every single day with performance that far surpasses that of traditional satellite internet and ground infrastructure limitations. Starlink delivers high-speed, low latency broadband internet to locations where access has been unreliable, expensive, or completely unavailable.
In this critical role, as a SOC/ASIC synthesis and front-end STA (Static Timing Analysis) engineer, you will be collaborating with architecture, timing, and logic design teams to make a crucial impact on delivering cutting edge SOCs for customers on Earth and beyond. We are looking for people who want to dive in and get their hands dirty and push the limits of what is possible through innovation, determination, and teamwork.
RESPONSIBILITIES:
Develop/modify/run RTL logic synthesis, formal verification, power intent verification and post synthesis timing validation flows
Execute low power design and physical synthesis, deploying knowledge of unified power format and power intent verification
Some logic design in Verilog/SystemVerilog and confirmation of quality of coding through LINT and clock domain crossing flows
Work with mixed signal IP/PLL/SerDes/PHY teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL
Integrate DFT/BIST insertion flows into synthesis flow
Full chip and block level timing constraint development, consistent full chip and block constraint partitioning
Timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)
Deploy and enhance methodology and flows related to timing constraint generation and verification and timing closure
Work closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs - generally bridging the RTL and place & route
Work with multi-disciplinary groups to make sure RTL/Netlists are on schedule and delivered with the highest quality by incorporating automated checks at every stage of the design process
Analysis of clock domain crossing paths at block and full chip level
BASIC QUALIFICATIONS:
Bachelor's degree in electrical engineering, computer engineering or computer science
5+ years of experience working as a synthesis and/or front-end STA engineer
PREFERRED SKILLS AND EXPERIENCE:
Experience in ASIC multimode constraint generation, constraint partitioning and timing closure in advanced nodes
Knowledge of deep sub-micron FinFET technology nodes (7nm and below) timing challenges, multi-corner and multimode timing closure, process variations (AOCV, POCV based STA), voltage drop aware STA, and clock reconvergence pessimism removal
Hands-on experience in industry standard physical synthesis and STA tools (Synopsys DC, Primetime or equivalent)
Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closure
Deep understanding of ASIC design flow, top-down and bottom-up design methodologies
Knowledge of low-power methodologies and leakage/dynamic power optimization flows and techniques
Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
Experience with high reliability design and implementations
Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
Must be willing to travel when needed (typically <10%)
Willing to work extended hours and weekends to meet critical deadlines, as needed
This position can be based in either Redmond, WA or Irvine, CA
ITAR REQUIREMENTS:
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.
