Duties : Responsible for building a coherent Field Programmable Gate Array (FPGA)-based accelerator used for accelerating memory access to very large Virtual Machines. Perform full end-to-end feature implementation from writing architecture/microarchitecture specification to RTL design, synthesis, timing closure and writing device driver code in C. Build test environment in Python to validate the feature on VMware ESXi hypervisor.
Requirements : Master's degree (U.S. or foreign equivalent) in Computer Science, Computer Engineering, Computer Information Systems, Information Technology, Electrical Engineering or a related technical/quantitative field and two (2) years of experience in job offered or related position. In the alternative, employer will accept a Bachelor's degree (U.S. or foreign equivalent) in Computer Science, Computer Engineering, Computer Information Systems, Information Technology, Electrical Engineering or a related technical/quantitative field and five (5) years of experience in job offered or related position.
Employer requires at least six (6) of the following skills gained through industry experience:
System Verilog;
Static Timing Analysis;
RTL design and synthesis;
Clock domain crossing;
Computer architecture and computer networking;
C programming and Python;
FPGA Design;
ASIC design or VLSI design, and post-silicon debug.
*Telecommuting permitted: work may be performed within normal commuting distance from the VMware office in Palo Alto, CA. Multiple Openings.
This job may require the candidate to travel and/or work from a facility that requires full vaccination prior to entry.
Category : Engineering and Technology
Subcategory: Software Engineering
Experience: Manager and Professional
Full Time/ Part Time: Full Time
Posted Date: 2022-05-23
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